Future power demands by wireless video applications are driving the need for innovations in power optimization both at the algorithmic and architectural level. One of the most power consuming modules for such applications is video coding. Architectures for MPEG4, the current standard for video coding, require low power compliance. Video data has a great possibility of having the presence of same magnitude for neighboring pixels. Preventing repetitive computations of these pixel values with intelligent data reuse is an effective power optimization technique. Furthermore, it can be observed that a large amount of data exists in video, which produce insignificant results. These data computations can also be prevented, by blocking the clock signals to the processing modules. Implementation of these design concepts in digital systems reduces the switching activity, which is the most important factor in power consumption.

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