ECE 443/543 Computer Architecture

 


 

Instructor

K. Vijayan Asari

Office

Kaufman Hall, Room 231L

Phone

757-683-3752

Email

vasari_at_odu_dot_edu

 

 

Office Hours

 

Tuesday

3:00 pm – 5:00 pm

Wednesday

3:00 pm – 5:00 pm

 

 

Teaching Assistant

Dwayne S. Blai

Email

dblai002_at_odu_dot_edu

Office Hours

Wednesday 10:00 am – 11:50 am (K 251)

 

 

Credits

3

 

 

Lectures

 

Time

9:00am  – 9:50 am Monday

9:00am  – 9:50 am Wednesday

9:00am  – 9:50 am Friday

Location

OCNPS 100

 

 

Prerequisites/Co-requisites

ECE 341 Digital System Design

 

ECE 446 Microcontrollers

 

 

Course Description

The student is introduced to the basics of computer architecture design. The course entails studying methods of CPU and I/O design and using those methods for the design and simulation of a simple CPU.

 

Homework

Homework will be assigned every week except during the exam weeks and will be collected in the following week. Late submissions will not be accepted.

 

Project

The project will be a semester long project to design and simulate a computer. Teams will be broken up to design and implement the memory system, the CPU, and the controller. You will be expected to demonstrate the ability to work in a group for integration of a complete design.

 

Honor Code

Students are expected to follow the ODU Honor Code for all assignments and exams. Any violations will be dealt with strictly according to university policy. However, this is also a course, which requires a lot of interaction, and sharing of ideas is encouraged. But all work that you turn in with your name on it should reflect your work, not someone else's. If at any time you have a question about whether you are violating the Honor Code, please ask me to make sure.

 

Disabilities

Students who have documented disabilities in accordance with university guidelines will be provided appropriate opportunities if the documentation is brought to the instructor's attention.

 

Course Outline

Basic computer organization, stored program concept, instruction set architecture, CPU structure, a CISC processor, MC68000 architecture, instruction set, addressing mode, a RISC processor, SPARC architecture, Processor design, 1-bus micro architecture, multi-bus architecture, data path implementation, control unit design, machine exceptions, Pipelining, instruction level parallelism, microprogramming, Memory system design, components of the memory system, memory module, dynamic RAM interface, hierarchical memory systems, cache memory, virtual memory, memory management unit, I/O systems, programmed I/O, interrupts, direct memory access, Parallelism in uniprocessor systems, organization of multiprocessor systems, communication in multiprocessor systems.

 

Course Description for Graduate Students - ECE 543

Each graduate student will make a 15 minutes presentation on an advanced topic in computer architecture and the class will discuss the ideas.