Milestones: subgroup I, subgroup II
 

• 8/25/2008:          

Introduction

Milestone 1 - board test (demonstrate that the UP-1 board is functional)

• 9/1/2008:            Labor Day, no class.

Project 1 (RLE): Analyze and draft your own RLE algorithm. Turn in the proposal for your compression algorithm along with analysis of worst and best case scenarios. The report should also briefly discuss the potential methods for implementation.

Milestone 2 - Project 2 (IHE): Simulate IHE technique with specific steps (C++/Matlab/Java etc.). Turn in your program with a report explaining the outcome of your simulation.

• 9/8/2008:

Milestone 2 - Project 1 (RLE): Simulate your algorithm with test images (C++/Matlab/Jave etc.). Turn in your program with a summary on compression ratio.

Project 2 (IHE): Analyze potential methods to calculate image histogram and transformation on functional level in hardware perspective.

• 9/15/2008:          

Milestone 3 - Develop communication protocol for the system: How would you send the image (pixel by pixel, block by block, etc.)? How do you know if it’s the end of the image, etc? The protocol should minimize overhead cost (delay) per transaction.

Turn in a formal group report of your protocols, including discussion on performance, its strength and weakness.

• 9/22/2008:         

Continue with communication interface, hardware design, GUI design.

• 9/29/2008:         

Continue with communication interface, hardware design, GUI design.

• 10/6/2008:         

Milestone 4

Subgroup I: Demonstrate serial communication and handshaking communication from (A) to (C) by sending 16 bytes of data.

Subgroup II: Demonstrate handshaking communication and serial communication from (C) to (E) by sending 32 bytes of data.

• 10/13/2008:       Fall Holiday, no class

Hardware implementation (consider the discussions from milestone 2): you may optimize your design based on the bottleneck of the system but keep in mind that the interface of RLE and IHE architectures should permit binding of two engines for concurrent processing. This step ensures easy system integration later on.

• 10/20/2008:         

Milestone 5 – Hardware implementation/simulation of your architecture. Turn in a brief formal report summarizing the simulation results of the components and core engines (RLE & IHE).  GUI demonstration with EXCEL plug-in functionality (Be able to plot a graph from your GUI)

• 10/27/2008:

Hardware simulation and GUI demo cont.

Hardware test of the algorithm.

• 11/3/2008:    

System integration I: (A) to (C) and (C) to (E).

• 11/10/2008: 

Milestone 6: Demonstrate GUI (A) to FPGA (C) for subgroup I, FPGA (C) to GUI (E) for subgroup II with consideration of your communication protocol for at least 16 bytes of data.

• 11/17/2008:       

System integration II (core engines + system integration I):

Separate applications (Project 1 and 2)

Both RLE and IHE engines in parallel

• 11/24/2008:       

System integration II cont.

• 12/1/2008:       

Final demonstration of integrated system (Overall project)

• (Final):

Final Report, Formal Presentation (12:30 – 3:30 pm in K230)

Please Note: There is no penalty in being ahead of schedule!! It is expected that each student spends 10 to 15 hours a week on this project in order to achieve the project goals. You may also resubmit/re-demonstrate your work if it shows significant improvement.