Project Overview:
 

The goal of this semester's ECE 489W project is to develop, design, build, test and demonstrate an integrated system for a specific application. You can choose one of the following applications for your project: (1) Run Length Encoding (RLE) or (2) Image Histogram Equalization (IHE) (Note: each group will work on ONE project only). Your working system will consist of two computers, two microcontrollers and one FPGA connected as shown in the Figure below.
 

The two microcontrollers are the communication gateways between the FPGA and two computers. Users will be able to interact with the system through a Graphical User Interface (GUI) in both computers (A and E).  The 8-bit bitmap images are loaded properly in (A) according to necessary attributes in the bmp header structure and sent to (C) for processing through the communication gateway (B). The main processing work for RLE (Project 1) and IHE (Project 2) is done in the FPGA board (C); however, the mapping on the last step of IHE process may be performed on (E).  The results are sent to (E) for display and analysis through the communication gateway (D). The basic GUI inputting commands in two end-user computers include:

• Loading and displaying images on (A) and (E).

• Transmitting the image to the UP-1 board for processing (A)

• Receiving the result from UP-1 board (E)

• Compute and display histogram graph on (A), and display the histogram obtained from (C) on (E) (for Project 2 only).

• Reconstructing and displaying the image from the returned RLE encoded data bytes (Project 1 only) (E)

• Additional GUI commands direct returned image coefficients/information to an EXCEL spreadsheet to record compression efficiency, time elapsed during the compression/decompression process (Project 1 only) (E).

The project will be divided into a series of milestones. Each milestone will require design, simulation, or verification for one or more components of the overall system. This project is intended to introduce and/or reinforce the following concepts:

• Top-down digital system design

• Computer-aided digital circuit design and simulation

• EPLD hardware usage and device programming

• Microcontroller interfacing

• Handshaking communication

• Digital circuit prototyping and debugging

• GUI development

• Serial communication

• System integration

All the associated digital circuitry, which makes up the system, will be implemented using the FLEX-10K20 chip. All simulation and device programming will be done using Altera's MAXPLUS2 logic design and simulation software, which supports schematic capture, AHDL (Altera Hardware Description Language), and VHDL (VHSIC Hardware Description Language). All necessary test and verification software and GUI development will be written in Visual C++.   Students will work in teams of four. Each team will be assigned to 2 lab stations in KDH 229/230. Each team will be assigned a lab kit, which includes an Altera experimental board with power supply and a ByteBlaster cable. Purchase of some additional parts (chips, ribbon cables, connectors, sockets, replacements for blown chips, etc.) will be required, as necessary. Also, it is assumed that each team member has a M68HC11 EVBU. Specific goals for the project are as follows:

• Develop a compression algorithm for 8-bit bitmap images based on RLE (Project 1 only)

• Understand the standard Image Histogram Equalization technique (Project 2 only)

• Design and simulate the algorithm/technique using MAXPLUS2 tools.

• Implement the algorithm/technique circuit on the FLEX-10K20 chip

• Design and implement the handshaking communication interface with M68HC11

• Develop a GUI interface

• Develop serial communication interface with PC

• Design and implement a communication protocol for the system

• Integrate all components (PC, M68HC11 and FLEX-10K20 chip) to form a working system

• Record and display results (graphical form)

• Write a formal final report to document the project.