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Objective
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The main
objective of this course is to provide an introduction to modern VLSI design.
The course deals with advanced logic and system design along with circuit
design. The most rewarding aspect of this course is that it puts together
previously learned basics on circuit design, logic design, and digital
architecture design to understand the tradeoffs between the different levels
of abstraction.
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Course Description
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This
course focuses on the design and synthesis of Very Large Scale Integrated (VLSI)
chips using CMOS technology for complex digital systems using integrated
circuit cells as building blocks and employing hierarchical design methods.
Design issues at layout, schematic, logic and RTL levels will be studied.
Commercial design software will be used for laboratory exercises. An overview
of VLSI computer-aided design (CAD) tools and theoretical concepts in VLSI
architectures and algorithms will also be discussed.
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Course Outline
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This
course is designed to provide undergraduate and graduate students in
electrical and computer engineering the ability to design and synthesis VLSI
chips using CMOS technology focusing towards the development of an
Application Specific Integrated Circuit. Topics: introduction, design tools,
the CMOS transistor, fabrication, layout and design rules implementing logic
in CMOS, design of adders, dynamic CMOS logic high speed adders and ALUs,
CMOS transistor theory, circuit characterization, delay estimation, CMOS
performance optimization, clocking strategies, other building blocks and
memory, control design, electrical effects, introduction to design
verification, introduction to testing, design of high performance circuits,
low power design high performance processor design, introduction to timing
verification, introduction to formal verification, verification of large
designs, design for testability, design of asynchronous circuits, future
trends
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Textbook
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Jan
M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic, Digital
Integrated Circuits – A Design Perspective
Prentice
Hall, 2003
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Supplementary Textbook
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John
P. Uyemura, Physical Design of CMOS Integrated Circuits Using L-EDIT
PWS
Publishing Co., 1995
(Contains the student version of L-EDIT)
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References
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Wayne
Wolf, Modern VLSI Design – System-on-Chip Design
Prentice Hall, 2002
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Neil H.
E. Weste, Kamran Eshraghian, and Micheal John Sebastian, Principles of
CMOS VLSI Design - A Systems Perspective
Addison Wesley, 2001
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Ken
Martin, Digital Integrated Circuit Design
Oxford University Press, 2000
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S. M.
Kang and Y. Leblebici, CMOS Digital Integrated Circuits - Analysis and
Design
McGraw-Hill, 1999
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J.P.
Uyemura, CMOS Logic Circuit Design
Kluwer Academic, 1999
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R.J.
Baker, H.W. Li, D.E Boyce, CMOS Circuit Design, Layout and Simulation
IEEE Press, 1998
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M.
Sarrafzadeh, An Introduction to VLSI Physical Design
McGraw-Hill,
1996
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Homework
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Homework
will be assigned every week except during the midterm and the final exam.
Solutions will be posted after the due date.
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Exams
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There
will be one mid-term exam and one comprehensive final exam. One may use the
textbook during an exam if they are kept free of any additional
writings.
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Project
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This is
a project-oriented course in which the students will be designing and
evaluating one of the following digital circuits: an adder/subtractor, a
multiplier, a ring counter, an ALU. Weekly assignments will be in the form of
design of the cells for the project.
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Laboratory
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VLSI Systems Laboratory
- KAUF 200
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Related Links
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L-EDIT
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SPICE
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MOSIS
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L-Edit
(Student Version)
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L-Edit
(Help)
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Grading Policy for Undergraduate Students - ECE495
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Homework
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30
%
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Midterm
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20
%
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Final
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30
%
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Project
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20
%
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Course
Description for Graduate Students - ECE595
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Each graduate
student will make a 15 minutes presentation on a key topic in advanced VLSI
design and the class will discuss the ideas. Students will also be
designing and evaluating an integrated system-on-a-chip in a team project.
Project will include developing the specification of the product,
performing an analysis of its feasibility, developing the detailed design,
writing a report on the design and making a presentation to the class
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Additional References
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IEEE
Transactions on VLSI Systems
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IEEE
Transactions on Circuits and Systems
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IEEE
Journal of Solid State Circuits
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The
Journal of VLSI Signal Processing-Systems for Signal, Image, and Video
Technology,
Kluwer Academic
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Wai-Kai
Chen, The VLSI Handbook, CRC Press, 2000
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V. G.
Oklobdzija, High Performance System Design, IEEE Press, 1999
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M. J.
S. Smith, Application Specific Integrated Circuits, Addison
Wesley, 1997
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A.
Chandrakasan, W. J. Bowhill and F. Fox, Design of High Performance
Microprocessor Circuits, IEEE Press, 2001
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Keshab
K. Parhi, VLSI Digital Signal Processing Systems: Design and
Implementation, Wiley, 1999
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H. J.
Ray Liu and Kung Yao, High-Performance VLSI Signal Processing
Innovative Architectures and Algorithms –
Algorithms
and Architectures (Volume-1), Wiley, 1997
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H. J.
Ray Liu and Kung Yao, High-Performance VLSI Signal Processing
Innovative Architectures and Algorithms –
Systems
Design and Applications (Volume 2), Wiley, 1997
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Grading Policy for Graduate Students - ECE595
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Homework
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20
%
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Midterm
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20
%
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Final
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30
%
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Project
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20
%
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Term
Paper
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10%
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Honor Code
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Students
are expected to follow the ODU Honor Code for all assignments and exams. Any violations
will be dealt with strictly according to university policy. However, this is
also a course, which requires a lot of interaction, and sharing of ideas is
encouraged. But all work that you turn in with your name on it should reflect
your work, not someone else's. If at any time you have a question about
whether you are violating the Honor Code, please ask me to make sure.
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Disabilities
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Students
who have documented disabilities in accordance with university guidelines will
be provided appropriate opportunities if the documentation is brought to the
instructor's attention.
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Course Syllabus
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Module 1.
Introduction:
digital systems and VLSI, system specification, behavior model, register transfer
level design, logic level design, circuit level design, device level design,
motivation and overview
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Module 2.
Transistors and layout: MOS (FET) transistor, fabrication process, structure
of the transistor, static behavior, dynamic behavior, design procedure, wires
and vias, design rules, layout design and tools
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Module 3.
The inverter:
definitions and properties, static behavior, dynamic behavior, power and
energy consumption, static CMOS inverter, power consumption and power-delay
product, effects of technology scaling
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Module 4.
Logic gates:
static CMOS design, ratioed logic, pass-transistor logic, dynamic CMOS
design, noise consideration in dynamic design, power consumption in CMOS
gates, switching activity of a logic gate, low power CMOS design
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Module 5.
Sequential circuits: latches and flip-flops, static sequential circuits, master-slave
and edge-triggered flip-flops, dynamic sequential circuits, dynamic two-phase
flip-flops, clocking strategies, advanced clocking analysis
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Module 6.
Subsystem design: subsystem design principles, pipelining, datapaths in digital
processor architectures, arithmetic circuits, adders, multipliers and
shifters, logic design considerations, programmable logic arrays,
field-programmable gate arrays
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Module 7.
Interconnects:
capacitive parasitics, modeling interconnect capacitance, capacitance and
performance in CMOS, resistive parasitics, modeling and scaling of
interconnect resistance, inductive parasitics, packaging, thermal
considerations
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Module 8.
Timing issues in digital circuits: clock skew and sequential circuit performance,
single-phase edge-triggered clocking, two-phase master-slave clocking,
clocking styles, on-chip clock generation and distribution
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Module
9.
Design methodologies: design analysis and simulation, design verification, timing
verification and functional verification, implementation approaches,
cell-based design methodology, array-based implementation approaches, design
synthesis, circuit synthesis, logic synthesis and architecture synthesis,
validation and testing, test procedure, design for testability, test-pattern
generation
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Term Paper Topics - ECE595
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CMOS
Scaling for High Performance and Low Power Applications
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Minimizing
Power Consumption in Digital CMOS Circuits
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Trends
in Low Power RAM Circuit Technologies
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CMOS
Circuit Speed and Buffer Optimization
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Clocking
Schemes for High-Speed Digital Systems
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Functional
Verification of System on Chips
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Register
Transfer Operation Analysis During Data Path Verification
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Logic
Design of Asynchronous Circuits
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VLSI
Implementation of 2-D Discrete Wavelet Transform
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A
Reconfigurable Architecture for Wireless Image Compression
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Low Power
Solutions to Wireless Applications
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Design
of an On-Chip Test Pattern Generator
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Reconfigurable
Computing for DSP
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VLSI
Array Architectures for Vector Quantization
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Partitioning
Sequential Circuits for Low Power
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Algorithmic
Aspects in VLSI Design
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Hybrid
Reconfigurable Processors
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Low
Power Realization of Digital Filters
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Implementation
of Multiplierless Digital Filters
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VLSI
Implementation of Adaptive Delta-Sigma Modulator
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Integrated
Memory/Logic Architecture for Image Processing
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VLSI
Design of Low Power Floating Point Accumulator
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Enhancement
Techniques for Adders
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Estimation
and Optimization of Switching Activity
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Advanced
Embedded Processor Circuit Design
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Estimating
and Modeling On-Chip Wiring Delays
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Dynamically
Programmable Gate Arrays
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Summer 2003 Schedule
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Mid-Term:
June 11
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Term
Paper Presentation: July 14
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Final
Exam: July 16
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