EET 310
Last updated 10/05/12
Errata Sheet for
Digital Logic Circuit Analysis and Design
First Edition
By Victor P. Nelson, et al.
| Chapter 3 Errata | |
| Pg 175, Ex. 3.3 | The second step is reached by performing T7a on the ABD +BD' |
| Pg 178, Table (b) | There are two blocks marked 7. Change lowest to 6. |
| Pg 179, list 2/3rds down | There should be a sigma in front of the min-term list |
| Pg 180, Ex. 3.4 | There should be a sigma in front of the min-term list |
| Pg 182, 4th line from the bottom | There should be a sigma in front of the min-term list |
| Pg 206, 3rd line from the bottom | Replace y3 with y1 |
| Pg 218, Ex. 3.25 | There should be a sigma in front of the min-term list |
| pg 240,Prob 40-55 | Use K-maps unless otherwise specified |
| Pg 241, Prob. 3.60 | Variable E is missing from both Switching lists |
| Chapter 4 Errata | |
| Pg 252 | The 1st sentence in the 74138 paragraph refers to a 74138 vice 73138 |
| Pg 253 Fig. 4.8(d) | G1 should be active high, A, B, C should also be active High. |
| Pg 255 Fig. 4.9(d) | The inputs A - D should be active High |
| Pg 256 Ex. 4.2 |
Should read "...implementations 2 and 4.." vice "...implementations 2 and 3.." |
| Pg 258 Fig 4.13(c) | The K-map should not have a 1 in min-term 0. |
| Pg 267 Fig 4.21(a) and (c) | Enable input E1 should be labeled EI |
| Pg 272 Fig 4.25(d) | W should be Active Low (have bubble) |
| Pg 273 Fig 4.26(c) | Remove the inversion bubbles from the NAND gates from E2-E15. These should be AND gates. |
| Pg 275 Fig 4.27(d) | The top enable in the figure should be named STROBE vice STRONG |
| Pg 275 Fig 4.27(e) | Label 1G and 2G enables as Active Low (have bubbles). The correct pin number for the 1Y output is 7; The 2Y output should be labeled as pin 9. |
| Pg 276 Fig 4.28(a) | Label pin 4 output as '1Y' and pin 14 input as '4A' |
| Pg 277 Fig 4.29(b) | Switch the order of S1 and S0 in the embedded truth table since S1 should be the MSB |
| Pg 278 Fig 4.30(b) | W should be Active Low (have bubble) |
| Pg 280 Fig 4.32 caption and Figure 4.32(b). | Change the lower case x to capital X for consistency with the example |
| Pg 280 Fig 4.32(b) | W should be Active Low (have bubble) |
| Pg 282 Fig 4.34 | The Y should be a W |
| Pg 320 Prob. 4.11 |
While this is not necessarily a mistake,
it is confusing. Remember that the 0 input line is assumed. In this case, just to keep thing from being confusing, delete the 0 in each switching list and the corresponding one in each input list of the two equations. (a) (1,2,...,9)=(0,0,0,0,0,1,1,1,1) (b) (1,2,...,9)=(0,0,0,1,0,0,0,1,0)
|
| Pg 322 Prob. 4.23 | (Eight connections are required: two for the NAND circuit and six for the MUX). Consider B to be the MSB for the MUX. Assume Q and R as inputs to the NAND gate circuit. |
| Pg 327 Prob. 4.41 | Change "(Hint: Use the cascade inputs to compare the two least significant digits; use one AND gate.)" to read "(Hint: Use the cascade inputs to compare the two most significant digits.)" |