EET 310
Last updated 11/26/12
Errata Sheet for
Digital Logic Circuit Analysis and Design
First Edition
By Victor P. Nelson, et al.
| Chapter 5 Errata | |
| Pg 380 Prob. 5.1(b) |
Should read "(as in Fig.5.7 with two product lines and one output added)" (only 1 extra product is really needed but I'm feeling generous) MUST USE DON'T CARES where appropriate for ANY CREDIT! Rember that Excess three is not defined above 9. |
| Pg 380 Prob. 5.1(c) | Change the word ROM to PROM. As with all PROMS, you MUST program all product lines even if not used. |
| Pg 380 Prob. 5.1(d) |
Should read "(as in Fig.5.30 with one output with its associated three product lines added)" MUST USE DON'T CARES where appropriate for ANY CREDIT! Rember that Excess three is not defined above 9. |
| Pg 380 Prob. 5.1 | Since the student is actually drawing the circuit, the line "Remember to specify...and PAL" should be deleted. |
| Pg 381 Prob. 5.2(a) | Use a 74154 Decoder for part a. |
| Pg 381 Prob. 5.2(a) | One gate per function, max fan-in is 6 inputs with the exception of f1 with a max fan-in of 7. |
| Pg 381 Prob. 5.2(b) Referring to Fig 5.7 used by the problem | Do not add any additional AND lines. In fact, you are only allowed to use 5 (five) product lines. Remove the E input line. |
| Pg 381 Prob. 5.2(c) | Change the word ROM to PROM. As with all PROMS, you MUST program all product lines even if not used. |
| Pg 381 Prob. 5.3 | Change the word ROM to PROM in both locations|
| Chapter 6 Errata | |
| Pg 398, Figure 6.15(c) | Delete the NOT gate associated with the Rnot input. THe label on the gate input should still be Rnot. |
| Pg 402, Eqn bottom third of page | Change last term from DC to DQ |
| Pg 406, Figure 6.22(b) | The arc from state 1 back to state 1 should be labeled 'd0' vice '0d' |
| Pg 408, Figure 6.25(b) |
The diagram name should be JK, not JR. |
|
Pg 410 Fig 6.28(b) |
1. D input is labeled with a Q.
It should be labeled with a D (duh!)
2. The Clock input is labeled with a Q. It should be labeled with as CLK (double duh!) 3. The label '76 which is near the Q output should be in the center of the model and should be a '74 instead. |
| Pg 411, Fig 6.30(a) | Labels 'tPHL and tPLH' at the bottom of the timing diagram should be swapped. |
| Pg 411, Last sentence on the page | Change "listed in Fig 6.30b as 0 ns" to "listed in Fig. 6.30b as 40ns and 25ns, respectively." |
| Pg 412, 1st sentence | Change "..output Q at the exact instant..." to read "output Q at either 40ns or 25ns from the exact instant..." |
| Pg 420, middle of page | Change the capacitor value from C = 3.125 microfarad to C = 0.1067 microfarad. |
| Pg 427, Prob. 6.11 |
Change the SN7476
to SN7476A.
The 7476A is neg edge triggered and has active low Pre's and Clr's. |
| Pg 429, Fig. P6.13 | The D flip-flop should be positive edge triggered, not negative edge triggered. |
| Pg 430, Fig. P6.26 |
Remove the (d) beneath the FF. |