EET330

Errata Sheet for
Digital Logic Circuit Analysis and Design
First Edition
By Victor P. Nelson, et al.

Chapter 7 Errata
Pg. 437. Fig 7.3(b) under the table heading 'Outputs'	The time should read t_n+8 instead of t_n+8 (the +8 should be part of the subscript)
Pg 439 End of line 11	Change 'flip-flips' to 'flip-flops'
Pg 444 Fig. 7.6d	Data input F waveform should have an H under its pulse vice a L. In following paragraph, the data stream should be (11110101)
Pg 457 Line 15.	The subscript for the second clear line should be 0(2) instead of O2 (zero instead of O)
Pg. 466 Fig. 7.19(c).	Fix 3 errors on the wired driven by the Clear' signal near the bottom left of the figure. 1. Change the inverter driven by Clear' to a buffer by adding an inversion bubble to its input. 2. Remove the 1st dot to the right on the wire driven by this inverter. (The inverter output should not be connected to the vertical wire driven by the AND gate below it.) 3. Find the vertical wire connected to the upper 3 flip-flop CLR inputs. This should also be connected the the wired driving the bottom flip-flop CLR input, and not to the wire immediately below it (i.e. move the vertical wire and dot up from the feedback wire driven by the QD output)
Pg. 473 Fig. 7.23	Below the logic diagram, change (a) to (c). Also, the lower Q output of flip-flop C in that diagram should have an inversion bubble (Q bar output)
Pg. 492 Fig. 7.36(c)	In the logic diagram, at the left bottom, the AND gate whose inputs are Strobe (10) and Clock (9) should have inversion bubbles on both inputs.
Pg. 498 Prob. 7.1	The problem refers to Figure 4.29. This should be changed to Figure 4.34.
Pg. 500 Prob. 7.15	The problem refers to Problems 7.8, 7.10, and 7.12. These should be Problems 7.9, 7.11, and 7.13.
Pg. 500 Prob. 7.16	The problem refers to Problems 7.9, 7.11, and 7.13. These should be Problems 7.10, 7.12, and 7.14.
Pg. 500 Prob. 7.16	The problem refers to Figure 7.34b and then to Figure 7.34. These should be fig 7.34 and Fig 7.34c, respectively.
Chapter 8 Errata
Chap. 8 State Tables	The author combines state tables and K-maps into a single figure. DO NOT DO THAT, even when told to by the problem statement. Do as is done in class. A single state table with multiple output columns which you use K-maps to simplify.
Chap. 8 HW problems	In problems where an INPUT string (X) is given without attaching the input to some time sequence: Always have the input pulses change in the middle of the low portion of the clock cycle. This is to help me grade as well as removing questions about setup and hold times.
Chap 8 HW problems	In A,B,C problems, you do not have to find the requested item in the order in which is was requested. However, you need to place it in your paper to turn-in to me in that order.
Pg 508 3rd para.	Replace Figure 8.1B with just Fig. 8.1
Pg 511 Caption 8.11a	Caption should read "for the circuit of Fig 8.8(a)" vice Fig 8.4(a)
Pg 514 Figure 8.14a	The 0 and 1 are transposed.
Pg 526	The Subsection heading "Sequence Recogizers" should read "Sequence Recognizers".
Pg 532 Figure 8.30	In the K-map for R2, change the entry in the top row (row 00), right column (col x=1) from '1' to '0'.
Pg 574 Prob. 8.18	Change "For the following circuit..." to read " For the following state table..."
Chapter 9 Errata
Pg 623 Prob. 9.10, 2nd line	Change "using the given state assignment" to "using each of the three unique state assignments." , and then delete the state assignment given next to the state table.