Vision and Image Processing Systems (VIPS)

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Hardware Development

Design of a high performance embedded system for real-time enhancement of color video stream (uniform darkness)

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Design of a high performance embedded system for real-time enhancement of color video stream (nonuniform darkness)

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HARDWARE DESIGN CAPABILITIES

Design Modules
Design of log and anti-log computational modules
Quadrant symmetry design approach for 2-D convolution module
Design of an efficient multiplier-less architecture for multi-dimensional convolution
Hardware module for normalized cross-correlation computation
Multilane architecture for modular-PCA implementation
Design of custom logic for video interface modules
Design of CORDIC based trigonometric functional modules
Unidirectional CORDIC modules for asynchronous applications
VLSI architecture for pre-computation of rotation bits in unidirectional Flat-CORDIC
VLSI efficient discrete time cellular neural network processor

Application Specific Architectures
Systolic implementation of feedforward neural networks for pattern recognition
Parallelo-pipelined design approach for nonlinear enhancement of color images
Pipelined architecture for distortion correction in wide-angle camera images
High performance architecture for multi-sensor image fusion
High storage capacity architecture for pattern recognition using an array of Hopfield neural networks
Hardware implementation of Fuzzy-ART based image compression
Vector processor based architecture for gradient and normal computation in real-time volume rendering
A parallel VLSI architecture for real-time segmentation of images with complex background environment
A generalized cellular neural network architecture for high storage capacity pattern recognition
A multilevel architecture for FPGA based implementation of feed-forward neural network for pattern recognition
A modular architecture for a recurrent neural network for character recognition
Systolic array implementation of block based Hopfield neural network for pattern association
System level design of real time face recognition architecture based on composite PCA
A fully pipelined architecture for barrel-distortion correction based on back mapping and linear interpolation
A flexible and efficient hardware architecture for real time face recognition based on eigenface appraoch

Low Power Design Approach
Neighborhood dependency considerations for low-power design
Switching activity control (logic level) in low-power digital design
Data dependency considerations in low power design of discrete cosine transform architecture